In general, a delay locked loop (DLL) is used to perform synchronization between digital signals, such as between an external clock data or between external and internal clocks, in a semiconductor device, computer system or the like.
A conventional DLL apparatus related to the DLL has been disclosed in Korean Patent Publication No. 2004-95981.
The aforementioned conventional DLL apparatus employs two replica delay units.
That is, the conventional DLL apparatus generally includes a first loop generating a rising clock and a second loop generating a falling clock. The phase difference between a reference clock input through a clock buffer from each of the loops and a clock fed back through a replica delay unit is detected by a phase detector. A delay is corrected in accordance with the detected result, and a clock is locked in the corrected state.
In general, rising and falling clocks are applied to the two loops, and a digital DCC synchronizes the rising edges of the two clocks with phases opposite to each other.
FIG. 1 illustrates the concept of a conventional digital DCC.
If clock signals CLK, /CLK are input, a reference clock REF is generated using these clock signals CLK, /CLK. The reference clock REF is delayed in a first loop to be changed as a rising clock R_CLK and then delayed in a second loop to be changed as a falling clock F_CLK. Since the rising and falling clocks R_CLK and F_CLK are signals with opposite phases and different pulse widths (tck/2−□ and tck/2+□), the rising edges of the two clocks are set to each other, and the pulse widths of the two clocks is adjusted through half phase blending. Accordingly, an output clock CLK_OUT with a duty ratio of 50% is generated.
The aforementioned conventional DLL circuit uses a dual loop and has a configuration related to a replica delay for each loop. Further, both loops performs operations before a DCC operation is started. However, circuits related to the replica delay, such as a replica delay unit, a phase detector, a dummy digital circuit and a dummy load which are included in a loop (a loop corresponding to a falling clock), are not used after a clock is corrected and a DCC operation is then started.
Therefore, the conventional DLL circuit has a problem in that unnecessary circuits exist after an DCC operation is started, so that a current is unnecessarily consumed and a design area for the unnecessary circuits is more required.
Further, there is a problem in that an instantaneous current is consumed when a replica delay unit corresponding to a falling clock is changed in an off state, so that a jitter is produced and an additional locking time in accordance with the jitter is required.